1. Field of the Invention
The present invention relates generally to chip carrier packages for semi-conductor integrated circuit chips and, more particularly, to a thermally enhanced homogeneous chip carrier package for integrated circuit chips.
2. Description of Related Art
It is conventional in the electronic industry to encapsulate one or more semiconductor devices such as integrated circuit chips in chip carrier packages. In doing so, heat dissipation can become an important design consideration. Chip carrier packages usually seal a chip or chips within insulative plastics or resins. This protects the chip from environmental hazards as well as providing a means for electrically and mechanically attaching the chip to an intended device. A primary focus in the design of such a chip carrier package where heat dissipation is a concern is to provide the chip with adequate protection from the external environment and to provide an adequate heat conduction conduit to carry heat away from the chip during operation.
Prior art approaches to such chip carrier packages include two major design areas. The first area is the provision for adequate protection from the external environment. The second area is the provision of a heat sink or other heat dissipation means for the chip. These areas may both be seen in designs for total encasement chip carrier packages (TE package). The TE package generally includes a lead frame having a chip mounting pad, an integrated circuit chip which is attached to the chip mounting pad, a plurality of fragile wires which connect the chip to the lead frame, and a thermoset plastic which totally encases the lead frame, the chip and the plurality of fragile wires. It may also include a heat sink (HS) or similar heat dissipation means. The TE package alone has several problems which arise from the thermoset plastic's direct contact with the chip and the plurality of fragile wires. First, the thermoset plastic is in direct contact with the plurality of fragile wires, which connect the chip to the lead frame. The molding process may cause a disruption of the planarity or spacing of the fragile wires, which can produce electrical shorting of the plurality of fragile wires, thus resulting in chip failure or damage. Second, different coefficients of thermal expansion exist for the chip, the lead frame, the plurality of fragile wires and the thermoset plastic. Materials having different coefficients of thermal expansion expand and contract at different rates during temperature variations. Temperature variations are produced during the molding process of the TE package, during final solder attachment of the TE package to the intended device board and during the operation of the chip within the TE package. The temperature variations provide the possibility for disassociation of the thermoset plastic from the chip and the plurality of fragile wires. Disassociation of the thermoset plastic from the chip and the plurality of fragile wires produces chip failure and/or damage resulting from wire stress failure or wire bond connection failure. The temperature variations further provide the possibility for the formation of voids. Third, the thermoset plastic utilized in the manufacture of the TE package exhibits hygroscopic properties. The hygroscopic properties of the TE package allow moisture to enter and accumulate in the formed voids. High temperatures are required during the final solder attachment of the TE package to the intended device. The high temperatures can convert the moisture, located within the formed voids, into steam, thereby expanding and cracking the TE package or the chip.
Addressing now heat dissipation for TE packages, a variety of prior art techniques have been utilized. The most conventional technique of heat dissipation in the electronic industry is the use of a heat sink. Such devices have been used in both small and large electronic units, the most common of which being consumer dimmer switches. With the complexity of small, sophisticated semiconductor devices, other problems arise which are exacerbated by the requirement to encapsulate the chip. The partial solution to these problems may be seen in a variety of prior art patents. One such approach is seen in U.S. Pat. No. 4,888,449 to Crane et al. The Crane et al. approach utilizes a base member having an expanded surface area, such as grooves, to provide an additional area for heat transfer. Another approach is seen in U.S. Pat. No. 4,887,149 to Romano, which teaches the use of a metal base plate heat sink mounted to a suitable external heat sink. The criticality of heat dissipation may thus be seen by the utilization of such heat dissipation approaches. Problems of course arise by the utilization of metal slugs disposed in direct association with the chip when the metal slug must be encapsulated in the plastic package therearound. The encapsulation of the chip is, however, of primary import, which leads to the problem of the differences in the thermal coefficient of expansion between the materials. One approach to overcoming the problem of differential thermal coefficients of expansion is the utilization of the plastic material itself as a heat dissipation member. This approach is set forth and shown in U.S. Pat. No. 5,254,500 wherein a plurality of molded members upstand from the top of the plastic package for direct heat dissipation from the chip encapsulated therein.
Another prior art approach for designing a chip carrier package to provide adequate protection from the external environment is a cavity package. The cavity package generally includes a lead frame having a plurality of lead members and a chip mounting pad, an integrated circuit chip attached to the chip mounting pad, a plurality of fragile wires which connect the chip to the plurality of lead members, a thermoset plastic which is formed around the lead frame and the chip mounting pad in such a manner as to provide a cavity, and a thermoset molded lid which is attached to the cavity by a thermoset adhesive. The cavity package has several problems associated with its manufacture. First, some of the plurality of lead members have their planarity compromised during the process of molding or injecting the thermoset plastic around the lead frame and the chip mounting pad. Each one of the plurality of lead members which has its planarity compromised increases the difficulty in connecting an associated fragile wire from the chip to the compromised lead member. Second, during the molding or injecting process, the chip mounting pad and the plurality of lead members may also be partially, or in some cases, totally, covered with the thermoset plastic material, causing extensive cleaning steps to remove the thermoset plastic material prior to connecting the plurality of fragile wires. Molding apparatus systems have been designed to address certain of these issues. However, the molding apparatus systems are expensive and require costly maintenance. Third, the thermoset plastic which is utilized in the manufacture of the cavity package exhibits hygroscopic properties. The hygroscopic properties of the thermoset plastic allow moisture to enter the cavity. Chemical leaching is produced from the contact of the moisture with the thermoset plastic within the cavity. Leached chemicals, within the cavity, can be in contact with the plurality of fragile wires and/or chip. The leached chemicals can result in the shorting of the plurality of fragile wires, thus producing chip failure. High temperatures are generated within the cavity during the process of attaching the cavity package to an intended device and during the operation of the chip. The generated high temperatures convert moisture within the cavity to steam, thereby expanding and cracking the thermoset molded lid and/or damage to the chip.
Other design issues are present in the prior art with regard to these semiconductor packaging approaches. This is because not all TE packages or cavity packages utilize lead frame arrays. The utilization of leadless circuit carrying insulating substrates has found approval in the semiconductor industry and may in certain instances further complicate heat dissipation issues by further reducing the amount of heat that will be carried away from the chip by the lead frame itself. For example, it is well known that heat generated in a semiconductor chip is dissipated to some extent through the leads extending from the integrated circuit package. When a leadless circuit carrying substrate is utilized, this avenue of heat dissipation is further limited although metal surface traces do carry away some heat when said traces are properly exposed.
A prior approach for a leadless chip carrier package which does not specifically address chip heat dissipation is set forth in as shown in U.S. Pat. No. 5,241,133 assigned to Motorola Inc. This patent teaches a leadless pad array chip carrier package wherein a protective plastic cover is transfer molded about the semiconductor device covering substantially all the top side of a printed circuit board with the bottom side having an array of solder pads which may include solder balls. The leadless pad array chip carrier package comprises a leadless circuit carrying insulating substrate being adapted for the mounting of a semiconductor device on one side thereof. The underside includes a plurality of surface mount solder pads electrically connected to the semiconductor device by means of plated through holes extending through the leadless circuit carrying substrate. The holes are positioned away from the solder pads. The assembly further includes a protective cover consisting of a resin transfer molded about the semiconductor device.
As stated above, resin coated surfaces are not always acceptable for end users of semiconductor devices and moisture infiltration is a constant concern with regard to the fabrication of all chip carrier packages. Differentials in the thermal coefficient of expansion between resin coatings and circuit substrates can be a problem due to the nonhomogeneous material interface therebetween. Any nonhomogeneity can subject the package to thermal cracking and comprise an area for moisture infiltration. Chip carrier packages having the advantages of certain prior art devices, such as integral heat sink assemblies, but constructed of a single homogenous material would therefore be a marked advantage over the prior art.
It would be an advantage therefore to have a thermally enhanced, homogeneous chip carrier package including a heat sink assembly (HC-HS package) for conventional lead frame and land grid array (LGA) and ball grid array (BGA) assemblies. The present invention provides such a package with a chip mounting cavity, heat sink and electrical contact points disposed on a circuit substrate in LGA and BGA assemblies which utilize the same heat sink for the various integral attachments of the HC package. Since the various integral attachments such as a cavity lid may all be comprised of the same thermoplastic as the HC-HS package, chemical bonding or fusing of the integral attachments to the HC-HS package may be utilized to provide protection of the chip from the external environment. The HC-HS package of the present invention eliminates many of the prior art problems associated with semiconductor heat sink assemblies and chip packages having different coefficients of thermal expansion therein. The present design also reduces the possibility of moisture entering the vicinity of the chip either through the package material or around the heat sink.